1. Field of the Invention
The present invention relates to a semiconductor device suitable for an IGBT (Insulated Gate Bipolar Transistor), and more particularly to an improvement to reduce an ON-state voltage.
2. Description of the Background Art
FIG. 70 is a sectional front view showing a structure of a semiconductor device according to the prior art which is a background of the present invention. FIG. 71 is a sectional view taken along the line K--K in FIG. 70. An device 150 according to the prior art comprises a SOI (Silicon On Insulator) wafer. The SOI wafer includes a silicon substrate 151, a silicon oxide film (a substrate insulation film) 152 formed on the silicon substrate 151, and an n.sup.- -type silicon layer (an active layer or a SOI layer) 153 formed on the silicon oxide film 152.
A p-type base layer 154 and an n-type buffer layer 156 are selectively formed apart from each other over an upper principal surface of the n.sup.- -type silicon layer 153. An n.sup.+ -type emitter layer 155 is selectively formed on an upper principal surface of the p-type base layer 154. A p.sup.+ -type collector layer 157 is selectively formed on an upper principal surface of the n-type buffer layer 156.
An emitter electrode 170 is connected across an upper principal surface of the n.sup.+ -type emitter layer 155 and that of the p-type base layer 154. A collector electrode 171 is connected to an upper principal surface of the p.sup.+ -type collector layer 157. A gate electrode 173 is provided opposite to the upper principal surface of the p-type base layer 154 with a gate insulation film (not shown) interposed therebetween. In other words, the device 150 comprises a "transverse (or lateral)" and n-channel type IGBT.
An isolation trench 161 is formed around the IGBT. An isolation electrode 163 is buried in the isolation trench 161 with an isolation insulation film 162 interposed therebetween. A circuit element which is not shown is formed in a region of the n.sup.- -type silicon layer 153 provided opposite to the IGBT with the isolation trench 161 interposed therebetween. The circuit element is an device portion for controlling the IGBT, for example. Differently from the IGBT acting as a power element, only a current having a small magnitude flows in the circuit element. The isolation trench 161 is provided in order to isolate the IGBT in which a current having a great magnitude flows from the circuit element which operates with the current having a small magnitude.
In recent years, a dielectric isolation type HVIC (High Voltage Integrated Circuit) having high-speed switching characteristics and less parasitic bipolar operation has vigorously been developed as a transverse type power device. The device 150 corresponds to an example in which a dielectric isolation is implemented by a SOI wafer and a trench isolation (the isolation trench 161).
When using the device 150, a positive voltage for the emitter electrode 170 is usually applied to the collector electrode 171 through a load. In this state, if a positive voltage which exceeds a predetermined threshold voltage is applied to the gate electrode 173, a channel region Ch defined in a surface portion of the p-type base layer 154 opposite to the gate electrode 173 becomes conductive so that electrons are injected from the n.sup.+ -type emitter layer 155 to the n.sup.- -type silicon layer 153.
More specifically, an electronic current Jn flows from the n.sup.+ -type emitter layer 155 to the n.sup.- -type silicon layer 153 (In the drawing, a direction of the electronic current Jn represents that of a flow of a positive electric charge). Accordingly, a hole is injected from the p.sup.+ -type collector layer 157 to the n.sup.- -type silicon layer 153. As a result, conductivity modulation is caused so that an electric resistance is lowered in the n.sup.- -type silicon layer 153. Therefore, a main current (collector current) is caused to flow from the collector electrode 171 to the emitter electrode 170. More specifically, the IGBT is brought into a conductive state (an ON state).
When a zero voltage or a negative voltage is applied to the gate electrode 173, the channel region Ch becomes non-conductive so that the injection of the electrons from the n.sup.+ -type emitter layer 155 to the n.sup.- -type silicon layer 153 is stopped. As a result, the conductivity modulation in the n.sup.- -type silicon layer 153 dissipates. Consequently, the flow of the main current is stopped. In other words, the IGBT is brought into a cut-off state (an OFF state). In the IGBT described above, a magnitude of the main current is controlled according to a voltage applied to the gate electrode 173.
As an example, the IGBT provided in the device 150 according to the prior art shown in FIGS. 70 and 71 will be described below. In the IGBT, a voltage drop is caused in the vicinity of the channel region Ch in the ON state so that a voltage drop is great between the collector electrode 171 and the emitter electrode 170 in the ON state, that is, an ON-state voltage is high. Furthermore, a hole current Jh passes through a transverse resistor (or lateral resistor) R of the p-type base layer 154. Therefore, a latch-up tolerance is low.
Such troubles are more or less caused in a MOS transistor as well as the IGBT, and are outstanding problems to be solved in semiconductor device represented by these elements (IGBT and MOS).